Surface topography in semiconductor integrated circuit manufacturing is increasingly important in the manufacture of multi-level semiconductor devices. The degree of planarization of a surface is recognized to be important in the patterning of subsequently formed features since the increasingly small critical dimensions require substantially planar surface to accurately transfer patterned features within design tolerances through a mask or reticle by passing radiation through the mask to a radiation sensitive surface such as a photoresist. The non-planarity of the surface is frequently magnified in subsequent material layer formation and photo-patterning processes.
For example, when depositing a polymeric layer of material, including a photoresist, the polymer is generally blanket deposited reflecting a topography in the deposited layer including protruding features on the surface such as metal lines or gate electrodes as well as penetrating features such as trench lines openings and Via openings.
Referring to FIG. 1A is shown an example of the effect that penetrating features such as Via openings have on material deposition. For example, Via openings 16A, 16B, 16C, and 16D are shown formed in a dielectric layer 15 in a portion of the process wafer substrate 17A having a relatively high density of Via opening features. In contrast, Via 16E is shown in a portion of the process wafer substrate 17B, separated in space from wafer portion 17A as indicated by lines e.g., 12, having a relatively low density of Via opening features. In prior art processes form forming dual damascene features, for example in a Via first process, a Via opening is first created followed by deposition and etchback of a polymeric layer e.g., 18, to a level where the polymer partially fills the Via opening to protect the Via in a subsequent trench etching process where an overlying trench opening encompassing one or more Vias is etched to form a dual damascene structure. In the process of depositing a layer of material, for example a polymeric layer 18 over the Via openings, the relatively higher density of the Via opening features in portion 17B of the process wafer substrate consumes a relatively larger portion of the deposited polymer, resulting in a relatively thinner polymer layer 18 overlying the Via openings in contrast with portion 17B having relatively fewer Via openings and producing in a relatively thicker polymer layer 18 over the feature opening e.g., 16E.
Referring to FIG. 1B, subsequently, in an etchback process, the etch back process produces polymer plugs e.g., 18A, 18B, 18C, 18D respectively filling varying portions of the Vias e.g., 16A, 16B, 16C, 16D which may vary in plug height among each other and be significantly different with respect to plug heights e.g., 18E filling Vias e.g., 16E in relatively less dense areas of the process wafer e.g., 17B. As a result of the nonuniform plug heights partially filling the Vias, a subsequent etching step to form the trench portion of a dual damascene structure will result in exposure of an intervening etch stop layer providing inadequate Via protection in the etching process or the formation of polymeric etching residues forming a Via fence at an upper portion of the plug. In particular, high aspect ratio Vias require uniform etching profiles including preventing formation of unetched residues around the Via openings during anisotropic etching of an overlying trench structure in a dual damascene formation process. The formation of Via fences detrimentally affect subsequent processes including adhesion/barrier layer deposition and metal filling deposition frequently resulting in degraded device performance including electrical pathway open circuits. Consequently, time consuming and complicated additional etching processes are required to remove the Via fence or otherwise adjust the Via etching profile increasing processing costs and reducing throughput.
There is therefore a need in the semiconductor processing art to develop a method to reliably manipulate the topography of radiation sensitive polymeric containing layers including improving a planarity to improve subsequent processes including lithographic and etchback processes to achieve improved device reliability and electrical performance while reducing processing costs.
It is therefore an object of the invention to provide a method to reliably manipulate the topography of radiation sensitive polymeric containing layers including improving a planarity to improve subsequent processes including lithographic and etchback processes to achieve improved device reliability and electrical performance while reducing processing costs in addition to overcoming other shortcomings and deficiencies in the prior art.